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MD1210
High Speed Dual MOSFET Driver
Features
6ns rise and fall time with 1000pF load 2.0A peak output source/sink current 1.2V to 5V input CMOS compatible 4.5V to 13V total supply voltage Smart Logic threshold Low jitter design Two matched channels Outputs can swing below ground Low inductance package Thermally-enhanced package
General Description
The Supertex MD1210 is a high speed, dual MOSFET driver. It is designed to drive high voltage P and N-channel MOSFET transistors for medical ultrasound and other applications requiring a high output current for a capacitive load. The high-speed input stage of the MD1210 can operate from 1.2V to 5.0V logic interface with an optimum operating input signal range of 1.8V to 3.3V. An adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. The input logic levels may be ground referenced, even though the driver is putting out bipolar signals. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation. VDD1, VDD2, and VH should be connected to the positive supply voltage, and VSS1, VSS2, and VL should be connected to 0V or to Ground. The GND pin is the logic control input signal digital ground. The output stage is capable of peak currents of up to 2.0A, depending on the supply voltages used and load capacitance present. The OE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly, when OE is low, the outputs are disabled, with the A output high and the B output low. This assists in properly pre-charging the AC coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS transistor pair.
Applications
Medical ultrasound imaging Piezoelectric transducer drivers Nondestructive evaluation PIN diode driver CCD Clock driver/buffer High speed level translator
Typical Application Circuit
+12V VDD1 OE Level Shifter Level Shifter OUTA +100V 1F VDD2 VH 0.47F
INA
10nF 3.3V CMOS Logic Inputs VSS2 VL VH VDD2 10nF INB Level Shifter -100V To Piezoelectric Transducer
OUTB
Supertex TC6320TG
1F
MD1210
Gnd VSS1 VSS2 VL
MD1210
Ordering Information
DEVICE MD1210 Package Option 12-Lead 4x4x0.8pitch QFN MD1210K6-G
-G indicates package is RoHS compliant (`Green')
Absolute Maximum Ratings
Parameter VDD1,VDD2, VH - supply voltage VSS1,VSS2, VL - supply voltage Logic input levels Maximum junction temperature Storage temperature Operating temperature Value -0.5V to +13.5V 0V -0.5V to 7.0V +125C -65C to 150C -20C to 85C
Pin Configuration
12 10
1
9
3
7
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
4
QFN
(top view)
6
DC Electrical Characteristics
(Over operating conditions unless otherwise specified, VH = VDD1 = VDD2 = 12V, VL = VSS1 = VSS2 = 0V, VOE = 3.3V, TJ = 25C)
Sym VDD1, VDD2 VH VL IDD1Q IDD2Q IHQ IDD1 IDD2 IH VIH VIL IIH IIL VIH VIL RIN CIN JA JC
Parameter Supply voltage Output high supply voltage Output low supply voltage VDD1 quiescent current VDD2 quiescent current VH quiescent current VDD1 average current VDD2 average current VH average current Input logic voltage high Input logic voltage low Input logic current high Input logic current low OE Input logic voltage high OE Input logic voltage low Input logic impedance to GND Logic input capacitance Thermal resistance to air Thermal resistance to case
Min 4.5 VSS + 2.0 VOE - 0.3 0 1.2 0 12 -
Typ 0.55 0.88 6.6 23 20 5.0 47 7.0
2
Max 13 VDD VDD - 2.0 10 10 5.0 0.3 1.0 1.0 5.0 0.3 30 10 -
Units Conditions V V V mA A A mA mA mA V V A A V V K pF C/W C/W All inputs 1oz. 4-layer 3x4" PCB with thermal pad and thermal via array --For logic input OE For logic inputs INA and INB One channel on at 5.0Mhz, No load No input transitions -------
MD1210
Outputs (V
Sym RSINK RSOURCE ISINK ISOURCE
H
= VDD1 = VDD2 = 12V, VL = VSS1 = VSS2 = 0V, VOE = 3.3V, TJ = 25C)
Parameter Output sink resistance Output source resistance Peak output sink current Peak output source current
H
Min -
Typ 2.0 2.0
Max 12.5 12.5 -
Units Conditions A A ISINK = 50mA ISOURCE = 50mA -----
AC Electrical Characteristics (V
Sym tirf tPLH tPHL tPOE tr tf l tr - tf l l tPLH-tPHL l tdm Parameter Inputs or OE rise & fall time Propagation delay when output is from low to high Propagation delay when output is from high to low Propagation delay OE to outputs Output rise time Output fall time Rise and fall time matching Propagation low to high and high to low matching Propagation delay match
= VDD1 = VDD2 = 12V, VL = VSS1 = VSS2 = 0V, VOE = 3.3V, TJ = 25C)
Min -
Typ 7.0 7.0 9.0 6.0 6.0 1.0 1.0 2.0
Max 10 -
Units Conditions ns ns ns ns ns ns ns ns ns For each channel Device to device delay match CLOAD = 1000pF, see timing diagram Input signal rise/fall time of 2ns Logic input edge speed requirement
Logic Truth Table
Logic Inputs OE H H H H L INA L L H H X INB L H L H X OUTA VH VH VL VL VH Output OUTB VH VL VH VL VL
Timing Diagram
3.3V
Simplified Block Diagram
VDD1 VDD2 VH
50%
IN
0V
50%
OE
MD1210 OUTA
tPLH
90%
tPHL
90% 10%
INA
OUT
0V
10%
INB
OUTB
tr
tf
GND
3
VSS1
VSS2
VL
MD1210
Propagation Delay
Propagation Delay vs. Logic Voltage 10 Propagation Delay (ns)
2.0 VOE/2 VTH (volts) 1.5 1.0 0.6V 0.5
Logic Input Threshold
VTH vs. VOE
9.0
8.0
7.0 6.0
1
1.5
2 2.5 3 Logic Voltage (V)
3.5
0
1.0
2.0 4.0 3.0 VOE (volts)
5.0
Detailed Block Diagram
VDD1 VDD2 VH
OE
Level Shifter Level Shifter OUTA
INA
VSS2
VL VH
VDD2
INB
Level Shifter SUB
OUTB
GND
VSS1
VSS2
VL
4
MD1210
Application Information
For proper operation of the MD1210, low inductance bypass capacitors should be used on the various supply pins. The GND input pin should be connected to the digital ground. The INA, INB, and OE pins should be connected to their logic source with a swing of GND to logic level high, which is 1.2V to 5.0V. Good trace practices should be followed corresponding to the desired operating speed. The internal circuitry of the MD1210 is capable of operating up to 100MHz, with the primary speed limitation being the loading effects of the load capacitance. Because of this speed and the high transient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. The VSS1, VSS2, and VL pins should have low inductance feed-through connections directly to a ground plane. The power connections VDD1 and VDD2 should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the power leads. A common capacitor and voltage source may be used for these two pins, which should always have the same DC voltage applied. For applications sensitive to jitter and noise, separate decoupling networks may be used for VDD1 and VDD2. The VH and VL pins can draw fast transient currents of up to 2.0A, so they should be provided with an appropriate bypass capacitor located next to the chip pins. A ceramic capacitor of up to 1.0F may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. Pay particular attention to minimizing trace lengths and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistor in series with the output signal to obtain better waveform integrity at the load terminals. This will of course reduce the output voltage slew rate at the terminals of a capacitive load. Pay particular attention to the parasitic coupling from the driver output to the input signal terminals. This feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.2V even small coupled voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Be careful that the circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry.
Pin Description
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 Name Description INA VL INB GND VSS1 VSS2 OUTB VH OUTA VDD2 VDD1 OE Logic input. Controls OUTA when OE is high. Input logic high will cause the output to swing to VL. Input logic low will cause the output to swing to VH. Supply voltage for N-channel output stage. Logic input. Controls OUTB when OE is high. Input logic high will cause the output to swing to VL. Input logic low will cause the output to swing to VH. Logic input ground reference. Low side analog circuit and level shifter supply voltage. Should be at the same potential as VSS2. Low side gate drive supply voltage. Output driver. Swings from VH to VL. Intended to drive the gate of an external N-channel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTB will swing to VL turning off the external N-channel MOSFET. Supply voltage for P-channel output stage. Output driver. Swings from VH to VL. Intended to drive the gate of an external P-channel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTA will swing to VH turning off the external P-channel MOSFET. High side gate drive supply voltage. High side analog circuit and level shifter supply voltage. Should be at the same potential as VDD2. Output-enable logic input. When OE is high, (VOE + VGND)/2 sets the threshold transition between logic level high and low for INA and INB. When OE is low, OUTA is at VH and OUTB is at VL regardless of INA and INB
Note: 1.Thermal Pad and Pin#5 (VSS1) must be connected externally. 2. Index Pad and Thermal Pad are connected internally 5
MD1210
12-Lead 4x4x0.8pitch QFN Package Outline (K6)
D D/2 INDEX AREA (D/2 xE/2) 4 -B-
-A E/2
aaa C 2x
aaa C 2x TOP VIEW ccc C NX 0.08 C SIDE VIEW
A
A1
D2 D2/2
NXl
A3
E2/2
E
SEATING PLANE -C-
e 1
-B-
INDEX AREA (D/2 xE/2) 4
N
N-1
NXb
5 bbb C CA B
-A-
ddd BTM VIEW SEE DETAIL B
6
E2
MD1210
12-Lead 4x4x0.8pitch QFN Package Outline (K6)
Datum A or B 4
3 BB 1
l1
e
Terminal Tip 5
3
Sy m b o l Min D B SC E B SC e D2 E2 b l A A1 A3 L1 Is s u e 2.0 2.0 0.25 0.45 0.80 0.00 --0.03 A H ei g h t D i m en s i o n s No m 4.0 4.0 0.80 2.15 2.15 0.30 0.55 0.90 0.02 0.20 r ef --2.25 2.25 0.35 0.65 1.0 0.05 --0.15 Max
N CC DD 3 AA 3
N-1
B o t t o m ID Dim en s io n s AA .434 BB .434 CC .181 DD .181
To ler an c e o f Fo r m & Po s i t i o n aaa bbb ccc ddd Is s u e 0.15 0.10 0.10 0.05 A
Notes: 1. Dimensioning and tolerancing conform to ASME Y14.5m - 1994. 2. All dimensions are in millimeters, all angles are in degrees (O). 3. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC publication 95, SPP-002. Details of terminal #1 identifier are optional, but must be located within the zone indicated. The terminal #1 identifier may be either a mold or marked feature. 4. Depending on the method of lead termination at the edge of the package, pull back (L1) may be present. L minus L1 to be equal to or greater than 0.33mm. 5. Dimension B applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension B should not be measured in that radius area.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-MD1210 B011507
7

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